Energy Efficient Sensor Node Implementations

Abstract : In this paper, we discuss a low power embedded sensor node architecture we are developing for distributed sensor network systems deployed in a natural environment. In particular, we examine the sensor node for energy efficient processing-at-the-sensor. We analyze the following modes of operation; event detection, sleep, data acquisition, data processing modes using low power, high performance embedded technology such as specialized embedded DSP processors and low power FPGAs at the sensing node. We use compute intensive sensor node applications: an acoustic vehicle classifier (frequency domain analysis) and a video license plate identification application (learning algorithm) as a case study. We report performance, energy and total average power usage for our system designs and discuss the system architecture design trade offs.
Type de document :
Communication dans un congrès
8th International Symposium on Field-Programmable Gate Arrays (FPGA 2010), Feb 2010, Monterey, United States. 2010
Liste complète des métadonnées

https://hal.inria.fr/inria-00451689
Contributeur : François Charot <>
Soumis le : vendredi 29 janvier 2010 - 17:02:24
Dernière modification le : mercredi 11 avril 2018 - 01:56:49

Identifiants

  • HAL Id : inria-00451689, version 1

Citation

Jan Frigo, Eric Raby, Ed Rosten, Vinod Kulathumani, Christophe Wolinski, et al.. Energy Efficient Sensor Node Implementations. 8th International Symposium on Field-Programmable Gate Arrays (FPGA 2010), Feb 2010, Monterey, United States. 2010. 〈inria-00451689〉

Partager

Métriques

Consultations de la notice

296