High speed reconfigurable SWP operator for multimedia processing using redundant data representation

Abstract : For better performance and efficiency, high speed reconfigurable computation units are required in processor design. However the reconfiguration overheads like interconnection cost and reconfiguration time delay reduce the benefits of reconfigurable processors. At the same time within the arithmetic operators, the speed of operations on binary data cannot be increased beyond certain limits because of the inherited carry propagation at any stage of the addition. In this paper to address both reconfiguration and computation time issues, a high speed reconfigurable operator is proposed for multimedia applications. This operator provides reconfigurability at both the operation level (different multimedia oriented operations) and at the data size level (different pixel data sizes) through the use of multimedia oriented subword parallelism (SWP). The speed of the different arithmetic operations is improved through the use of a carry propagation free addition on the redundant data representation. For multimedia applications, this operator ensures reconfigurability with high resource utilization along with high speed operations.
Type de document :
Article dans une revue
Information Sciences and Computer Engineering, ISCE, 2010, 1 (1), pp.45-52. 〈http://www.ijisce.org〉
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https://hal.inria.fr/inria-00480330
Contributeur : Emmanuel Casseau <>
Soumis le : mardi 4 mai 2010 - 08:53:16
Dernière modification le : mercredi 16 mai 2018 - 11:23:26

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  • HAL Id : inria-00480330, version 1

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Shafqat Khan, Emmanuel Casseau, Daniel Ménard. High speed reconfigurable SWP operator for multimedia processing using redundant data representation. Information Sciences and Computer Engineering, ISCE, 2010, 1 (1), pp.45-52. 〈http://www.ijisce.org〉. 〈inria-00480330〉

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