Design Methodology for a High Performance Robust DVB-S2 Decoder Implementation

Abstract : The new Digital Video Broadcasting Satellite (DVBS2) standard is able to provide capacity gains of about 30% over the previous standard by using a powerfull Forward Error Correction (FEC) scheme based on very large LDPC codewords and BCH codes. The implementation of the DVB-S2 FEC decoder is a big challenge. The designer must deal with the overall design complexity and the decoding throughput in order to obtain a high decoding performance in terms of bit error rate (BER). We present in detail a complete design flow allowing a better understanding of the algorithm in terms of complexity, performance and its hardware implementation. We focus on complexity-performance trade-offs due to message quantizations and we compare its effects on several algorithm corrections used to check nodes for DVB-S2 decoding. The simulation results show that the best compromise between complexity and performance is obtained for the FOMS algorithm approximation.
Type de document :
Communication dans un congrès
13th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 2010), Sep 2010, Lille, France. 2010
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https://hal.inria.fr/inria-00480723
Contributeur : François Charot <>
Soumis le : mardi 4 mai 2010 - 17:41:09
Dernière modification le : mercredi 16 mai 2018 - 11:23:26

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  • HAL Id : inria-00480723, version 1

Citation

Florent Berthelot, François Charot, Charles Wagner, Christophe Wolinski. Design Methodology for a High Performance Robust DVB-S2 Decoder Implementation. 13th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 2010), Sep 2010, Lille, France. 2010. 〈inria-00480723〉

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