LV*: A Class of Lazy Versioning HTMs for Low-Cost Integration of Transactional Memory Systems

Abstract : Transactional memory (TM) promises to unlock parallelism in software in a safer and easier way than lock-based approaches but the path to deployment is unclear for several reasons. First of all, since TM has not been deployed in any machine yet, experience of using it is limited. While software transactional memory implementations exist, they are too slow to provide useful experience. Existing hardware transactional memory implementations, on the other hand, can provide the efficiency required but they require a significant effort to integrate in cache coherence infrastructures or freeze critical policy parameters. This paper proposes the LV* (lazy versioning and eager/lazy conflict resolution) class of hardware transactional memory protocols. This class of protocols has been implemented with ease of deployment in mind. LV* can be integrated with low additional complexity in standard snoopy-cache MESI-protocols and can be accommodated in a directory-based cache coherence infrastructure. Since the optimal conflict resolution policy (lazy or eager) depends on transactional characteristics of workloads, LV* supports a set of conflict resolution policies that range from LazEr – a family of Lazy versioning Eager conflict resolution protocols – to LL-MESI which provides lazy resolution. We show that LV* can be hosted in a MESI protocol through straightforward extensions and that the flexibility in the choice of conflict resolution strategy has a significant impact on performance.
Type de document :
Communication dans un congrès
IFMT'10 - Second International Forum on Next Generation Multicore/Manycore Technologies, Jun 2010, Saint Malo, France. 2010
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https://hal.inria.fr/inria-00492863
Contributeur : Ist Rennes <>
Soumis le : jeudi 17 juin 2010 - 12:31:14
Dernière modification le : lundi 20 juin 2016 - 14:10:32

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  • HAL Id : inria-00492863, version 1

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Anurag Negi, M. M. Waliullah, Per Stenstrom. LV*: A Class of Lazy Versioning HTMs for Low-Cost Integration of Transactional Memory Systems. IFMT'10 - Second International Forum on Next Generation Multicore/Manycore Technologies, Jun 2010, Saint Malo, France. 2010. 〈inria-00492863〉

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