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Performance Impact of Task Mapping on the Cell BE Multicore Processor

Abstract : Current multicores present themselves as symmetric to programmers with a bus as communication medium, but are known to be non-symmetric because their interconnect is more complex than a bus. We report on our experiments to map a simple application with communication in a ring to SPEs of a Cell BE processor such that performance is optimized. We find that low-level tricks for static mapping do not necessarily achieve optimal performance. Furthermore, we ran exhaustive mapping experiments, and we observed that (1) performance variations can be significant between consecutive runs, and (2) performance forecasts based on intuitive interconnect behavior models are far from accurate even for a simple communication pattern.
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https://hal.inria.fr/inria-00493924
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Submitted on : Monday, June 21, 2010 - 4:04:27 PM
Last modification on : Saturday, November 18, 2017 - 6:16:02 PM
Long-term archiving on: : Wednesday, September 22, 2010 - 6:13:40 PM

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  • HAL Id : inria-00493924, version 1

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Jörg Keller, Ana L. Varbanescu. Performance Impact of Task Mapping on the Cell BE Multicore Processor. A4MMC 2010 - 1st Workshop on Applications for Multi and Many Core Processors, Jun 2010, Saint Malo, France. ⟨inria-00493924⟩

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