Performance Impact of Task Mapping on the Cell BE Multicore Processor

Abstract : Current multicores present themselves as symmetric to programmers with a bus as communication medium, but are known to be non-symmetric because their interconnect is more complex than a bus. We report on our experiments to map a simple application with communication in a ring to SPEs of a Cell BE processor such that performance is optimized. We find that low-level tricks for static mapping do not necessarily achieve optimal performance. Furthermore, we ran exhaustive mapping experiments, and we observed that (1) performance variations can be significant between consecutive runs, and (2) performance forecasts based on intuitive interconnect behavior models are far from accurate even for a simple communication pattern.
Type de document :
Communication dans un congrès
Ana Lucia Varbanescu and Rob van Nieuwpoort and Anca Molnos. A4MMC 2010 - 1st Workshop on Applications for Multi and Many Core Processors, Jun 2010, Saint Malo, France. 2010
Liste complète des métadonnées

Littérature citée [15 références]  Voir  Masquer  Télécharger

https://hal.inria.fr/inria-00493924
Contributeur : Ist Rennes <>
Soumis le : lundi 21 juin 2010 - 16:04:27
Dernière modification le : samedi 18 novembre 2017 - 18:16:02
Document(s) archivé(s) le : mercredi 22 septembre 2010 - 18:13:40

Fichier

A4MMC-keller.pdf
Fichiers produits par l'(les) auteur(s)

Identifiants

  • HAL Id : inria-00493924, version 1

Collections

Citation

Jörg Keller, Ana L. Varbanescu. Performance Impact of Task Mapping on the Cell BE Multicore Processor. Ana Lucia Varbanescu and Rob van Nieuwpoort and Anca Molnos. A4MMC 2010 - 1st Workshop on Applications for Multi and Many Core Processors, Jun 2010, Saint Malo, France. 2010. 〈inria-00493924〉

Partager

Métriques

Consultations de la notice

100

Téléchargements de fichiers

90