Cache Tracker: A Key Component for Flexible Many-Core Simulation on FPGAs

Abstract : This paper presents a cache tracker, a hardware component to track the cache state of hundreds of caches serving processors modeled using threads on a single MIPS64 processor. This host-multithreading approach allows a single, low-cost FPGA to model large systems to allow quick and broad architectural exploration with reasonable simulation performance. The cache tracker stores all state in DRAM to allow maximum scalability in both number of processors and in cache sizes. We describe our approach of scalability versus simulation performance, our implementation in Bluespec SystemVerilog, and give a sample study of a parallel merge-sort over various processor numbers, cache sizes and arrangements.
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Communication dans un congrès
Omar Hammami and Sandra Larrabee. WARP - 5th Annual Workshop on Architectural Research Prototyping, Jun 2010, Saint Malo, France. 2010
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Jonathan Woodruff, Greg Chadwick, Simon Moore. Cache Tracker: A Key Component for Flexible Many-Core Simulation on FPGAs. Omar Hammami and Sandra Larrabee. WARP - 5th Annual Workshop on Architectural Research Prototyping, Jun 2010, Saint Malo, France. 2010. 〈inria-00494102〉

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