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Enabling Parallelization via a Reconfigurable Chip Multiprocessor

Abstract : While reconfigurable computing has traditionally involved attaching a reconfigurable fabric to a single processor core, the prospect of large-scale CMPs calls for a reevaluation of reconfigurable computing from the perspective of multicore architectures. We present ReMAPP, a reconfigurable architecture geared towards application acceleration and parallelization. In ReMAPP, parallel threads share a common reconfigurable fabric which can be configured for individual thread computation or fine-grained communication with integrated computation. The architecture supports both fine-grained barrier synchronization and fine-grained point-to-point communication for pipeline parallelization. The combination of communication and configurable computation within ReMAPP provides the unique ability to perform customized computation while data is transferred between cores, and to execute custom global functions after barrier synchronization. We demonstrate that ReMAPP achieves significantly higher performance and energy efficiency compared to hard-wired communication- only mechanisms, and over what can ideally be achieved by allocating the fabric area to more cores.
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https://hal.inria.fr/inria-00494289
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Submitted on : Tuesday, June 22, 2010 - 3:54:18 PM
Last modification on : Friday, June 11, 2021 - 5:12:08 PM
Long-term archiving on: : Friday, September 24, 2010 - 5:49:57 PM

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  • HAL Id : inria-00494289, version 1

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Matthew A. Watkins, David H. Albonesi. Enabling Parallelization via a Reconfigurable Chip Multiprocessor. Pespma 2010 - Workshop on Parallel Execution of Sequential Programs on Multi-core Architecture, Jun 2010, Saint Malo, France. ⟨inria-00494289⟩

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