A High Level Synthesis Flow Using Model Driven Engineering

Sébastien Le Beux 1, * Laurent Moss 1 Philippe Marquet 2, 3 Jean-Luc Dekeyser 2, 3
* Auteur correspondant
1 EPM - École Polytechnique de Montréal
2 LIFL - Laboratoire d'Informatique Fondamentale de Lille
3 DART - Contributions of the Data parallelism to real time
LIFL - Laboratoire d'Informatique Fondamentale de Lille, Inria Lille - Nord Europe
Abstract : Intensive Signal Processing (ISP) applications handle large amounts of data and are characterized by hierarchical and data parallel tasks, which manip- ulate multidimensional data arrays according to complex data dependencies. Performance requirements often preclude ISP applications from being im- plemented purely in software and instead call for using custom and efficient hardware accelerators. A hardware accelerator is an electronic design dedi- cated to the execution of a specific application. Its hardware architecture can be designed for a maximal parallelization of the algorithm needed to execute its application and for optimal execution support for regular and repetitive tasks. However, the complexity of hardware accelerators makes them difficult to manipulate at low abstraction levels (in a Hardware Description Language (HDL) for instance). The description of complex ISP applications is also error prone and tedious when using tools that constrain the number of dimensions of data arrays. High Level Synthesis (HLS) seeks to simplify the design of hardware accel- erators by describing applications at a high abstraction level and by generat- ing the corresponding low level implementation. Application specification is easier at a high abstraction level since hardware designers do not need to han- dle all low level implementation details. HLS thus aims to achieve algorithm- architecture matching by construction, through the automated synthesis of a hardware architecture for an application specified at a high level. The automatic generation of low level implementations drastically reduces non- recurring engineering costs and the time to market compared to hand-tuned implementations in HDL. For these reasons, HLS tools have been increasingly successful among the hardware designer community. This trend is followed by the continual integration of new capabilities and functionality in the tools. Therefore, successful HLS has to support rapidly evolving technologies and be maintainable in order to capitalize on efforts. We present some design challenges faced by HLS and how model-driven engineering can meet them.
Keywords : High Level Synthesis hardware accelerators Model Driven En- gineering intensive signal processing
Type de document :
Chapitre d'ouvrage
Gogniat, G.; Milojevic, D.; Morawiec, A.; Erdogan, A. Algorithm-Architecture Matching for Signal and Image Processing, 73, Springer, pp.253-274, 2010, Lecture Notes in Electrical Engineering, 978-90-481-9964-8
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Sébastien Le Beux, Laurent Moss, Philippe Marquet, Jean-Luc Dekeyser. A High Level Synthesis Flow Using Model Driven Engineering. Gogniat, G.; Milojevic, D.; Morawiec, A.; Erdogan, A. Algorithm-Architecture Matching for Signal and Image Processing, 73, Springer, pp.253-274, 2010, Lecture Notes in Electrical Engineering, 978-90-481-9964-8. 〈inria-00524821〉

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