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High level modeling of Partially Dynamically Reconfigurable FPGAs based on MDE and MARTE

Imran Rafiq Quadri 1 Samy Meftali 1, 2 Jean-Luc Dekeyser 1, 2 
1 DART - Contributions of the Data parallelism to real time
LIFL - Laboratoire d'Informatique Fondamentale de Lille, Inria Lille - Nord Europe
Abstract : System-on-Chip (SoC) architectures are becoming the preferred solution for implementing modern embedded systems. However their design complexity continues to augment due to the increase in integrated hardware resources requiring new design methodologies and tools. In this paper we present a novel SoC co-design methodology based on aModel Driven Engineering framework while utilizing the MARTE (Modeling and Analysis of Real-time and Embedded Systems) standard. This methodology permits us to model fine grain reconfigurable architectures such as FPGAs and allows to extend the standard for integrating new features such as Partial Dynamic Reconfiguration supported by modern FPGAs. The overall objective is to carry out modeling at a high abstraction level expressed in a graphical language like UML (Unified Modeling Language) and afterwards transformations of these models, automatically generate the necessary specifications required for FPGA implementation.
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Submitted on : Sunday, October 10, 2010 - 7:03:26 PM
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  • HAL Id : inria-00525008, version 1


Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. High level modeling of Partially Dynamically Reconfigurable FPGAs based on MDE and MARTE. Reconfigurable Communication-centric SoCs (ReCoSoC'08), Jul 2008, Barcelona, Spain. ⟨inria-00525008⟩



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