A Model based design flow for Dynamic Reconfigurable FPGAs

Imran Rafiq Quadri 1 Samy Meftali 1, 2 Jean-Luc Dekeyser 1, 2
1 DART - Contributions of the Data parallelism to real time
LIFL - Laboratoire d'Informatique Fondamentale de Lille, Inria Lille - Nord Europe
Abstract : As System-on-Chip (SoC) based embedded systems have become a de-facto industry standard, their overall design complexity has increased exponentially in recent years, necessitating the introduction of new seamless methodologies and tools to handle the SoC co-design aspects. This paper presents a novel SoC co-design methodology based on Model Driven Engineering and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard, permitting us to raise the abstraction levels and allows to model fine grain reconfigurable architectures such as FPGAs. Extensions of this methodology have enabled us to integrate new features such as Partial Dynamic Reconfiguration supported by Modern FPGAs. The overall objective is to carry out system modeling at a high abstraction level expressed in a graphical language like UML (Unified Modeling Language) and afterwards transformation of these models, automatically generate the necessary code for FPGA synthesis.
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International Journal of Reconfigurable Computing, Hindawi Publishing Corporation, 2009
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Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser. A Model based design flow for Dynamic Reconfigurable FPGAs. International Journal of Reconfigurable Computing, Hindawi Publishing Corporation, 2009. 〈inria-00525017〉

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