Skip to Main content Skip to Navigation

Multi-operand Decimal Adder Trees for FPGAs

Alvaro Vazquez 1, * Florent de Dinechin 1
* Corresponding author
1 ARENAIRE - Computer arithmetic
Inria Grenoble - Rhône-Alpes, LIP - Laboratoire de l'Informatique du Parallélisme
Abstract : The research and development of hardware designs for decimal arithmetic is currently going under an intense activity. For most part, the methods proposed to implement fixed and floating point operations are intended for ASIC designs. Thus, a direct mapping or adaptation of these techniques into a FPGA could be far from an optimal solution. Only a few studies have considered new methods more suitable for FPGA implementations. A basic operation that has not received enough attention in this context is multi-operand BCD addition. For example, it is of interest for low latency implementations of decimal fixed and floating point multipliers and decimal fused multiply-add units. We have explored the most representative proposals for multi-operand BCD addition and found that the resultant implementations in FPGAs are still very inefficient in terms of both area and latency when compared to their binary counterparts. In this paper we present a new method for fast and efficient implementation of multi-operand BCD addition in current FPGA devices. In particular, our proposal maps quite well into the slice structure of the Xilinx Virtex-5/Virtex-6 families and it is highly pipelineable. The synthesis results for a Virtex-6 device indicate that our implementations halve the area and latency of previous proposals, presenting area and delay figures close to those of optimal binary adder trees.
Document type :
Complete list of metadata

Cited literature [28 references]  Display  Hide  Download
Contributor : Alvaro Vazquez Connect in order to contact the contributor
Submitted on : Thursday, October 14, 2010 - 12:39:09 PM
Last modification on : Thursday, January 20, 2022 - 4:13:51 PM
Long-term archiving on: : Thursday, October 25, 2012 - 5:15:27 PM


Files produced by the author(s)


  • HAL Id : inria-00526327, version 1



Alvaro Vazquez, Florent de Dinechin. Multi-operand Decimal Adder Trees for FPGAs. [Research Report] RR-7420, INRIA. 2010, pp.20. ⟨inria-00526327⟩



Les métriques sont temporairement indisponibles