A Complete Design-Flow for the Generation of Ultra Low-Power WSN Node Architectures Based on Micro-Tasking

Abstract : Wireless Sensor Networks (WSN) are a new and very challenging research field for embedded system design automation, as their design must enforce stringent constraints in terms of power and cost. WSN node devices have until now been designed using off-the-shelf low-power microcontroller units (MCUs), even if their power dissipation is still an issue and hinders the wide-spreading of this new technology. In this paper, we propose a new architectural model for WSN nodes (and its complete design-flow from C downto synthesizable VHDL) based on the notion of micro-tasks. Our approach combines hardware specialization and power-gating so as to provide an ultra low-power solution for WSN node design. Our first estimates show that power savings by one to two orders of magnitude are possible w.r.t. MCU-based implementations.
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https://hal.inria.fr/inria-00554202
Contributor : Steven Derrien <>
Submitted on : Monday, January 10, 2011 - 2:39:12 PM
Last modification on : Wednesday, December 18, 2019 - 5:28:50 PM

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  • HAL Id : inria-00554202, version 1

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Adeel Pasha, Olivier Sentieys, Steven Derrien. A Complete Design-Flow for the Generation of Ultra Low-Power WSN Node Architectures Based on Micro-Tasking. Proc. of the 47th IEEE/ACM Design Automation Conference (DAC), Jun 2010, Anaheim, CA, USA, x-proceedings = yes, x-international-audience = yes, x-editorial-board = yes, x-in, United States. pp.693 - 698. ⟨inria-00554202⟩

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