Automatic Abstraction and Fault Tolerance in Cortical Microachitectures

Atif Hashmi 1 Hugues Berry 2, 3, 4 Olivier Temam 4 Mikko Lipasti 1
2 BEAGLE - Artificial Evolution and Computational Biology
LIRIS - Laboratoire d'InfoRmatique en Image et Systèmes d'information, Inria Grenoble - Rhône-Alpes, LBBE - Laboratoire de Biométrie et Biologie Evolutive, CarMeN - Cardiovasculaire, métabolisme, diabétologie et nutrition
4 ALCHEMY - Architectures, Languages and Compilers to Harness the End of Moore Years
LRI - Laboratoire de Recherche en Informatique, UP11 - Université Paris-Sud - Paris 11, Inria Saclay - Ile de France, CNRS - Centre National de la Recherche Scientifique : UMR8623
Abstract : Recent advances in the neuroscientific understanding of the brain are bringing about a tantalizing opportunity for building synthetic machines that perform computation in ways that differ radically from traditional Von Neumann machines. These brain-like architectures, which are premised on our understanding of how the human neocortex computes, are highly fault-tolerant, averaging results over large numbers of potentially faulty components, yet manage to solve very difficult problems more reliably than traditional algorithms. A key principle of operation for these architectures is that of automatic abstraction: independent features are extracted from highly disordered inputs and are used to create abstract invariant representations of the external entities. This feature extraction is applied hierarchically, leading to increasing levels of abstraction at higher levels in the hierarchy. This paper describes and evaluates a biologically plausible computational model for this process, and highlights the inherent fault tolerance of the biologically-inspired algorithm. We introduce a stuck-at fault model for such cortical networks, and describe how this model maps to hardware faults that can occur on commodity GPGPU cores used to realize the model in software. We show experimentally that the model software implementation can intrinsically preserve its functionality in the presence of faulty hardware, without requiring any reprogramming or recompilation. This model is a first step towards developing a comprehensive and biologically plausible understanding of the computational algorithms and microarchitecture of computing systems that mimic the human cortex, and to applying them to the robust implementation of tasks on future computing systems built of faulty components.
Type de document :
Communication dans un congrès
38th ACM/IEEE International Symposium on Computer Architecture, ISCA 2011, Jun 2011, San Jose, CA, United States. 2011
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Contributeur : Hugues Berry <>
Soumis le : jeudi 24 mars 2011 - 22:34:27
Dernière modification le : mardi 17 juillet 2018 - 15:49:35
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  • HAL Id : inria-00579771, version 1


Atif Hashmi, Hugues Berry, Olivier Temam, Mikko Lipasti. Automatic Abstraction and Fault Tolerance in Cortical Microachitectures. 38th ACM/IEEE International Symposium on Computer Architecture, ISCA 2011, Jun 2011, San Jose, CA, United States. 2011. 〈inria-00579771〉



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