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Modélisation UML/MARTE de SoC et analyse temporelle basée sur l'approche synchrone

Adolf Abdallah 1 Abdoulaye Gamatié 1 Jean-Luc Dekeyser 1 
1 DART - Contributions of the Data parallelism to real time
LIFL - Laboratoire d'Informatique Fondamentale de Lille, Inria Lille - Nord Europe
Abstract : System-on-Chip (Soc) are becoming very sophisticated. They require a huge amount of resources (processors, memories, etc.) to improve their execution performances in terms of execution time and energy. SoC development leads to a real challenge due to their complexity. This paper focuses on a high level design of these systems through a model-driven approach. We use the UML/MARTE profile dedicated to the Modelling and Analysis of Real Time Embedded systems. From user-defined models, temporal information are extracted for analyzing the system temporal properties. We consider the synchronous approach that favors formal validation.
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Submitted on : Friday, October 28, 2011 - 10:35:14 PM
Last modification on : Friday, February 4, 2022 - 3:14:47 AM

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Adolf Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser. Modélisation UML/MARTE de SoC et analyse temporelle basée sur l'approche synchrone. Revue des Sciences et Technologies de l'Information - Série TSI : Technique et Science Informatiques, 2011, Architecture des ordinateurs, 30 (9), pp.1089 -- 1114. ⟨10.3166/tsi.30.1089-1113⟩. ⟨inria-00637009⟩



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