Register constraints in ILP scheduling can be taken into account during the scheduling phase of a code. The complexity of this problem is very high. In this work, we present a new approach consisting in manipulating data dependence graphs to reduce the number of «potential» \vsa without assuming any schedule. We study theoretically the exact upper-bound of the register need for all valid schedules of a code¸: we call this limit the register saturation. It is used to build a modified data dependence graph such that any schedule of this graph will verify the register constraint- s and avoid introducing spill code. We study the case of Direct Acyclic Graphs and then we extend it to loops intended to software pipelining schedule. Experimental study shows that many DAGs and loops do not need register constraints during scheduling.