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Reconfigurable arithmetic for HPC

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Abstract

An often overlooked way to increase the efficiency of HPC on FPGA is to tailor, as tightly as possible, the arithmetic to the application. An ideally efficient implementation would, for each of its operations, toggle and transmit just the number of bits required by the application at this point. Conventional microprocessors, with their word-level granularity and fixed memory hierarchy, keep us away from this ideal. FPGAs, with their bit-level granularity, have the potential to get much closer. Therefore, reconfigurable computing should systematically investigate, in an application-specific way, non-standard precisions, but also non-standard number systems and non-standard arithmetic operations. The purpose of this chapter is to review these opportunities.
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Dates and versions

ensl-00758377 , version 1 (28-11-2012)

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  • HAL Id : ensl-00758377 , version 1

Cite

Florent de Dinechin, Bogdan Pasca. Reconfigurable arithmetic for HPC. Wim Vanderbauwhede and Khaled Benkrid. High-Performance Computing using FPGAs, Springer, 2013. ⟨ensl-00758377⟩
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