Skip to Main content Skip to Navigation

Sequential Multiplier with Sub-linear Gate Complexity

Anwar Hasan 1 Christophe Negre 2
2 DALI - Digits, Architectures et Logiciels Informatiques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, UPVD - Université de Perpignan Via Domitia
Abstract : In this article, we present a new sequential multiplier for extended binary finite fields. Like its existing counterparts, the proposed multiplier has a linear complexity in flip-flop or temporary storage requirements, but a sub-linear complexity in gate counts. For the underlying polynomial multiplication, the proposed field multiplier relies on the Horner scheme.
Complete list of metadata

Cited literature [14 references]  Display  Hide  Download
Contributor : Christophe Negre Connect in order to contact the contributor
Submitted on : Tuesday, June 26, 2012 - 1:50:03 PM
Last modification on : Friday, October 22, 2021 - 3:07:35 PM
Long-term archiving on: : Thursday, September 27, 2012 - 2:40:28 AM


Files produced by the author(s)


  • HAL Id : hal-00712085, version 1



Anwar Hasan, Christophe Negre. Sequential Multiplier with Sub-linear Gate Complexity. [Research Report] 2012, pp.12. ⟨hal-00712085⟩



Les métriques sont temporairement indisponibles