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Sequential Multiplier with Sub-linear Gate Complexity

Anwar Hasan 1 Christophe Negre 2
1 ECE - Department of Electrical and Computer Engineering [Waterloo]
2 DALI - Digits, Architectures et Logiciels Informatiques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier, UPVD - Université de Perpignan Via Domitia
Abstract : In this article, we present a new sequential multiplier for extended binary finite fields. Like its existing counterparts, the proposed multiplier has a linear complexity in flip-flop or temporary storage requirements, but a sub-linear complexity in gate counts. For the underlying polynomial multiplication, the proposed field multiplier relies on the Horner scheme.
Keywords : sub-linear gate complexity Binary polynomial multiplication sequential multiplier Horner scheme sub-linear gate complexity.
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https://hal.inria.fr/hal-00712085
Contributor : Christophe Negre <>
Submitted on : Tuesday, June 26, 2012 - 1:50:03 PM
Last modification on : Thursday, May 24, 2018 - 3:59:23 PM
Long-term archiving on: : Thursday, September 27, 2012 - 2:40:28 AM

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  • HAL Id : hal-00712085, version 1

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CNRS | UNIV-PERP | DALI | LIRMM | LARA | MIPS | UNIV-MONTPELLIER

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Anwar Hasan, Christophe Negre. Sequential Multiplier with Sub-linear Gate Complexity. [Research Report] 2012, pp.12. ⟨hal-00712085⟩

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