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Formal Verification of Fault Tolerant NoC-based Architecture

Abstract : Approaches to design fault tolerant Network-on-Chip (NoC) for System-on-Chip(SoC)-based reconfigurable Field-Programmable Gate Array (FPGA) technology are challenges on the conceptualisation of the Multiprocessor System-on-Chip (MPSoC) design. For this purpose, the use of rigorous formal approaches, based on incremental design and proof theory, has become an essential step in a validation architecture. The Event-B formal method is a promising formal approach that can be used to develop, model and prove accurately the domain of SoCs and MPSoCs. This paper gives a formal verification of a NoC architecture, using the Event-B methodology. The formalisation process is based on an incremental and validated correct-by-construction development of the NoC architecture.
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Contributor : Manamiary Bruno Andriamiarina Connect in order to contact the contributor
Submitted on : Tuesday, December 11, 2012 - 6:40:25 PM
Last modification on : Saturday, October 16, 2021 - 11:26:09 AM
Long-term archiving on: : Tuesday, March 12, 2013 - 3:52:39 AM


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  • HAL Id : hal-00763092, version 1


Manamiary Bruno Andriamiarina, Hayat Daoud, Mostefa Belarbi, Dominique Méry, Camel Tanougast. Formal Verification of Fault Tolerant NoC-based Architecture. First International Workshop on Mathematics and Computer Science (IWMCS2012), Mostefa BELARBI - University of Tiaret - Algeria, Dec 2012, Tiaret, Algeria. ⟨hal-00763092⟩



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