Some Hardware Aspects of the BESM-6 Design

Abstract : This paper very shortly describes some hardware solutions of central processor (CPU) of BESM-6. CPU had very deep instruction pipe with an associative buffer for instructions and an associative buffer for data with original protocol. Logical and storage elements used only domestic discrete components. Main logical unit based on differential amplifier with pyramid of rich diode logic and paraphase synchronization. Original construction without printed plate made wire connections very short and gave possibilities for direct access to every contacts and interchanging modules. All these solutions permitted to achieve high clock frequency, reliability and effective maintenance.
Type de document :
Communication dans un congrès
John Impagliazzo; Eduard Proydakov. 1st Soviet and Russian Computing (SoRuCom), Jul 2006, Petrozavodsk, Russia. Springer, IFIP Advances in Information and Communication Technology, AICT-357, pp.20-25, 2011, Perspectives on Soviet and Russian Computing. 〈10.1007/978-3-642-22816-2_3〉
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Soumis le : mardi 25 juillet 2017 - 11:43:09
Dernière modification le : mardi 25 juillet 2017 - 12:54:45

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V. Smirnov. Some Hardware Aspects of the BESM-6 Design. John Impagliazzo; Eduard Proydakov. 1st Soviet and Russian Computing (SoRuCom), Jul 2006, Petrozavodsk, Russia. Springer, IFIP Advances in Information and Communication Technology, AICT-357, pp.20-25, 2011, Perspectives on Soviet and Russian Computing. 〈10.1007/978-3-642-22816-2_3〉. 〈hal-01568415〉

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