Design Methodology for an All CMOS Bandgap Voltage Reference Circuit

Abstract : The Internet of Thing (IoT) has given rise to the integration of smart systems in the industrial, healthcare, and social environments. These smart systems are often implemented by system-on-chip (SoC) solutions that require power management units, sensors, signal processors, and wireless interfaces. Hence, an independent voltage reference circuit is crucial for obtaining accurate measurements from the sensors and for the proper operation of the SoC. Making, bandgap circuits indispensable in these types of applications. Typically, bandgap circuits are implemented using bipolar transistors to generate two voltages with opposite temperature coefficients (Complementary To Absolute Temperature – CTAT; Proportional do Absolute Temperature - PTAT) which are added resulting in a temperature independent voltage reference. The disadvantage of using bipolar devices is that the power supply voltage must be larger than the ON base-emitter voltage, resulting in voltages larger than 0.7 V. The low power demands of IoT and of technology scaling, have forced lower values for the power supply voltage and thus new bandgap circuits using only CMOS transistors have gathered increased interest. In these, the MOS transistors operate in the weak inversion region where its current has an exponential relation with its gate-to-source voltage, as in the bipolar devices. Making it possible to generate both the PTAT and the CTAT voltages and thus produce a temperature independent voltage reference. This paper describes a design methodology of an all CMOS bandgap voltage reference circuit, in which one of the transistors works in the moderate region and the other in the weak inversion, to achieve the lowest possible voltage variation with temperature. The circuit produces a voltage reference of 0.45 V from a minimum power supply voltage of 0.6 V, with a total variation of 1.54 mV, over a temperature range of −40 to 100°C, resulting in a temperature coefficient of 24 ppm/°C, and a power supply rejection ratio (PSRR) of −40 dB.
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Luis M. Camarinha-Matos; Mafalda Parreira-Rocha; Javaneh Ramezani. 8th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS), May 2017, Costa de Caparica, Portugal. Springer International Publishing, IFIP Advances in Information and Communication Technology, AICT-499, pp.439-446, 2017, Technological Innovation for Smart Systems. 〈10.1007/978-3-319-56077-9_43〉
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Ricardo Madeira, Nuno Paulino. Design Methodology for an All CMOS Bandgap Voltage Reference Circuit. Luis M. Camarinha-Matos; Mafalda Parreira-Rocha; Javaneh Ramezani. 8th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS), May 2017, Costa de Caparica, Portugal. Springer International Publishing, IFIP Advances in Information and Communication Technology, AICT-499, pp.439-446, 2017, Technological Innovation for Smart Systems. 〈10.1007/978-3-319-56077-9_43〉. 〈hal-01629561〉

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