Multiplierless Processing Element for Non-Power-of-Two FFTs

Abstract : This paper presents hardware-efficient building blocks for non-power-of-two Fast Fourier transform (FFT) algorithms. A reconfigurable unified multiplierless mixed radix-2/3/4/5 FFT design is proposed. In addition, standalone designs for the computation of the multiplierless radix-3 and radix-5 processing elements are illustrated. These architectures are based on Wingorad Fourier transform algorithm , which uses constant multipliers instead of general complex-valued multipli-ers. In this paper we propose to further reduce the hardware complexity by replacing the constant multipliers by shift-and-add structures. In addition, we show that the unified architecture is achieved by adding only a small number of multiplexers. The implementation results for field-programmable gate arrays (FPGAs) with Look-Up Table based logic are provided. In all of them, the proposed designs achieve significant reduction in area (around 30%) with respect to state of the art.
Type de document :
Pré-publication, Document de travail
2018
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https://hal.inria.fr/hal-01690832
Contributeur : Anastasia Volkova <>
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Dernière modification le : vendredi 23 novembre 2018 - 01:47:57
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  • HAL Id : hal-01690832, version 1

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Fahad Qureshi, Anastasia Volkova, Thibault Hilaire, Jarmo Takala. Multiplierless Processing Element for Non-Power-of-Two FFTs. 2018. 〈hal-01690832〉

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