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Conference Papers Year : 2017

Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays

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Abstract

Coarse-Grained Reconfigurable Arrays (CGRAs) have emerged as a powerful solution to speedup computationally intensive applications. Heterogeneous MPSoC architectures containing such reconfigurable accelerators have the advantage of providing high flexibility, power-efficiency, and high performance. However, CGRAs may suffer from a data access bottleneck. To mitigate this problem, we present a reconfigurable buffer architecture for CGRAs. Here, the buffers can be configured at runtime to select between different schemes for memory access, i.e., addressable RAMs or pixel buffers. We showcase the benefits of our approach by prototyping a heterogeneous MPSoC architecture containing a RISC processor and a class of CGRA called Tightly Coupled Processor Arrays (TCPAs). The architecture is prototyped in FPGA technology. For basic image processing algorithms, we demonstrate that our proposed buffer structures for system integration allow to increase the memory bandwidth utilization and allow for a performance improvement of up to 7% in comparison to state-of-the-art solutions for image processing.
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Dates and versions

hal-01854155 , version 1 (06-08-2018)

Licence

Attribution - CC BY 4.0

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Éricles Sousa, Frank Hannig, Jürgen Teich. Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays. 5th International Embedded Systems Symposium (IESS), Nov 2015, Foz do Iguaçu, Brazil. pp.218-229, ⟨10.1007/978-3-319-90023-0_18⟩. ⟨hal-01854155⟩
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