Full Text Documents

Search


Table of Contents
System Level Design from HW/SW to Memory for Embedded Systems
Marcelo Götz, Gunar Schirner, Marco Aurélio Wehrmeister, Mohammad Abdullah Al Faruque, Achim Rettberg
Front Matter

Cyber-Physical Systems


Ontological User Modeling for Ambient Assisted Living Service Personalization
Maurício Vargas, Carlos Pereira
3-14
Multi-Agent Based Implementation of an Embedded Image Processing System in FPGA for Precision Agriculture Using UAVs
Érico Nunes, Lucas Behnck, Carlos Pereira
15-26
Combining Service-Oriented Computing with Embedded Systems - A Robotics Case Study
Alexander Jungmann, Jan Jatzkowski, Bernd Kleinjohann
27-37
Integration of Robot Operating System and Ptolemy for Design of Real-Time Multi-robots Environments
Luis Costa, Alisson Brito, Tiago Nascimento, Thiago Bezerra
38-47

System-Level Design


Bit-Precise Formal Verification for SystemC Using Satisfiability Modulo Theories Solving
Lydia Jaß, Paula Herber
51-63
Timed Path Conditions in MATLAB/Simulink
Marcus Mikulcak, Paula Herber, Thomas Göthel, Sabine Glesner
64-76
Structural Contracts – Motivating Contracts to Ensure Extra-Functional Semantics
Gregor Nitsche, Ralph Görgen, Kim Grüttner, Wolfgang Nebel
77-87
Combining an Iterative State-Based Timing Analysis with a Refinement Checking Technique
Björn Koopmann, Achim Rettberg, Tayfun Gezgin
88-99

Multi/Many-Core System Design


Hierarchical Multicore-Scheduling for Virtualization of Dependent Real-Time Systems
Jan Jatzkowski, Marcio Kreutz, Achim Rettberg
103-115
Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs
Andrés Goens, Jeronimo Castrillon
116-127
Modeling and Analysis of SLDL-Captured NoC Abstractions
Ran Hao, Nasibeh Teimouri, Kasra Moazzemi, Gunar Schirner
128-141

Memory System Design


Taming the Memory Demand Complexity of Adaptive Vision Algorithms
Majid Sabbagh, Hamed Tabkhi, Gunar Schirner
145-158
HMC and DDR Performance Trade-offs
Paulo Santos, Marco Alves, Luigi Carro
159-171
Managing Cache Memory Resources in Adaptive Many-Core Systems
Gustavo Girão, Flávio Wagner
172-182

Embedded HW/SW Design and Applications


A UML Profile to Couple the Production Code Generator TargetLink with UML Design Tools
Malte Falk, Stefan Walter, Achim Rettberg
185-196
Rapid, High-Level Performance Estimation for DSE Using Calibrated Weight Tables
Kasra Moazzemi, Smit Patel, Shen Feng, Gunar Schirner
197-209
Low Latency FPGA Implementation of Izhikevich-Neuron Model
Vitor Bandeira, Vivianne Costa, Guilherme Bontorin, Ricardo Reis
210-217
Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays
Éricles Sousa, Frank Hannig, Jürgen Teich
218-229