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System Level Design from HW/SW to Memory for Embedded Systems 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015 Foz do Iguaçu, Brazil, November 3-6, 2015 |
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Conference papers
Combining an Iterative State-Based Timing Analysis with a Refinement Checking Technique
Abstract : The analysis of real-time properties is crucial in safety critical areas like in automotive applications. Systems have to work in a timely manner to offer correct services. Most of the applications in this domain are distributed over several computation units, inter-connected by bus systems. In previous works we have introduced a state-based analysis approach to validate end-to-end deadlines for distributed systems. The approach is based on the computation of the state spaces of all resources, such as processors and buses, in an iterative fashion. For this, abstraction and composition operations were defined to adequately handle task and resource dependencies. During the design process of a system changes occur typically on both the specification and implementation level, such that already performed analyses of the system have to be repeated. In this work, we extend our timing analysis with a refinement checking approach, detail when it is appropriate to be used, and compare the analysis times with the computation times to perform the refinement check.
Cited literature [18 references]
https://hal.inria.fr/hal-01854160
Contributor : Hal Ifip <>
Submitted on : Monday, August 6, 2018 - 3:10:12 PM
Last modification on : Monday, August 6, 2018 - 3:12:01 PM
Document(s) archivé(s) le : Wednesday, November 7, 2018 - 2:09:21 PM
Contributor : Hal Ifip <>
Submitted on : Monday, August 6, 2018 - 3:10:12 PM
Last modification on : Monday, August 6, 2018 - 3:12:01 PM
Document(s) archivé(s) le : Wednesday, November 7, 2018 - 2:09:21 PM
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