Skip to Main content Skip to Navigation
Conference papers

Systolic Array Based Accelerator and Algorithm Mapping for Deep Learning Algorithms

Abstract : As the depth of DNN increases, the need for DNN calculations for the storage and computing power of the underlying computing platform is increasing. In this work, we implement an accelerator on FPGA for deep learning algorithms (CNN and RNN). The core computing module of the accelerator is a 32 * 32 systolic array of PEs. A mapping method for variable size of CNN and RNN algorithms is proposed. The experiment result shows that the maximum power consumption of the accelerator is 7.5W@100Mhz, the peak performance is 0.2Tops/s, and the real performance is 7.6Mops@100Mhz when running the 1st layer of LeNet-5.
Document type :
Conference papers
Complete list of metadata

Cited literature [9 references]  Display  Hide  Download

https://hal.inria.fr/hal-02279547
Contributor : Hal Ifip <>
Submitted on : Thursday, September 5, 2019 - 1:30:54 PM
Last modification on : Thursday, September 5, 2019 - 1:35:35 PM
Long-term archiving on: : Thursday, February 6, 2020 - 1:43:30 AM

File

477597_1_En_16_Chapter.pdf
Files produced by the author(s)

Licence


Distributed under a Creative Commons Attribution 4.0 International License

Identifiers

Citation

Zhijie Yang, Lei Wang, Dong Ding, Xiangyu Zhang, Yu Deng, et al.. Systolic Array Based Accelerator and Algorithm Mapping for Deep Learning Algorithms. 15th IFIP International Conference on Network and Parallel Computing (NPC), Nov 2018, Muroran, Japan. pp.153-158, ⟨10.1007/978-3-030-05677-3_16⟩. ⟨hal-02279547⟩

Share

Metrics

Record views

87

Files downloads

104