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Worst-Case Reaction Time Optimization on Deterministic Multi-Core Architectures with Synchronous Languages

Nicolas Hili 1 Alain Girault 2, 3 Eric Jenn 1, 4
1 IRT Saint Exupéry - Institut de Recherche Technologique
2 UGA [2016-2019] - Université Grenoble Alpes [2016-2019]
3 SPADES - Sound Programming of Adaptive Dependable Embedded Systems
Inria Grenoble - Rhône-Alpes, LIG - Laboratoire d'Informatique de Grenoble
4 Thales AVS
Keywords : PRET Architecture Multi-core / many core platforms Synchronous Languages Inter-core synchronizations
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https://hal.inria.fr/hal-02400009
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Submitted on : Monday, December 9, 2019 - 12:35:21 PM
Last modification on : Wednesday, November 3, 2021 - 6:45:30 AM
Long-term archiving on: : Tuesday, March 10, 2020 - 5:39:05 PM

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LIG | INRIA | LIG-MFML-SPADES | IRT_SAINT-EXUPERY | CNRS | UGA | LIG_SIDCH

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Nicolas Hili, Alain Girault, Eric Jenn. Worst-Case Reaction Time Optimization on Deterministic Multi-Core Architectures with Synchronous Languages. 25th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'19), Aug 2019, Hangzhou, China. pp.10, ⟨10.1109/RTCSA.2019.8864570⟩. ⟨hal-02400009⟩

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