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Data-Aware Process Networks


With the emergence of reconfigurable FPGA circuits as a credible alternative to GPUs for HPC acceleration, new compilation paradigms are required to map high-level algorithmic descriptions to a circuit configuration (High-Level Synthesis, HLS). In particular, novel parallelization algorithms and intermediate representations are required. In this paper, we present the data-aware process networks (DPN), a dataflow intermediate representation suitable for HLS in the context of high-performance computing. DPN combines the benefits of a low-level dataflow representation-close to the final circuit-and affine iteration space tiling to explore the parallelization trade-offs (local memory size, communication volume, parallelization degree). We outline our compilation algorithms to map a C program to a DPN (front-end), then to map a DPN to an FPGA configuration (back-end). Finally, we present synthesis results on compute-intensive kernels from the Polybench suite.
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hal-03143777 , version 1 (17-02-2021)



Christophe Alias, Alexandru Plesco. Data-Aware Process Networks. CC 2021 - 30th ACM SIGPLAN International Conference on Compiler Construction, Mar 2021, Virtual, South Korea. pp.1-11, ⟨10.1145/3446804.3446847⟩. ⟨hal-03143777⟩
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