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Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches
Abstract : Multi-core chips have been increasingly adopted by the microprocessor industry. For real-time systems to exploit multi-core architectures, it is required to obtain both tight and safe estimates of worst-case execution times (WCETs). Estimating WCETs for multi-core platforms is very challenging because of the possible interferences between cores due to shared hardware resources such as shared caches, memory bus, etc. This paper proposes a compile-time approach to reduce shared instruction cache interferences between cores to tighten WCET estimations. Unlike [J. Yan and W. Zhang 08], which accounts for all possible conflicts caused by tasks running on the other cores when estimating the WCET of a task, our approach drastically reduces the amount of inter-core interferences. This is done by controlling the contents of the shared instruction cache(s), by caching only blocks statically known as reused. Experimental results demonstrate the practicality of our approach.
Cited literature [29 references]
https://hal.inria.fr/inria-00380298
Contributor : Damien Hardy Connect in order to contact the contributor
Submitted on : Thursday, April 30, 2009 - 2:04:26 PM
Last modification on : Wednesday, February 2, 2022 - 3:50:43 PM
Long-term archiving on: : Thursday, June 10, 2010 - 10:27:54 PM
Contributor : Damien Hardy Connect in order to contact the contributor
Submitted on : Thursday, April 30, 2009 - 2:04:26 PM
Last modification on : Wednesday, February 2, 2022 - 3:50:43 PM
Long-term archiving on: : Thursday, June 10, 2010 - 10:27:54 PM
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RR-6907.pdf
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