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Choosing Representative Slices of Program Execution for Microarchitecture Simulations: A Preliminary Application to the Data Stream

Thierry Lafage 1 André Seznec 1
1 CAPS - Compilation, parallel architectures and system
IRISA - Institut de Recherche en Informatique et Systèmes Aléatoires, Inria Rennes – Bretagne Atlantique
Abstract : Microarchitecture simulations are aimed at providing results representative of the behavior of a processor on an application. Due to CPU time constaints, only a few execution slices of a large application can be simulated. The aim of this paper is to propose a technique to choose a few program execution slices representative of the entire execution. Precise dynamic program behavior is gathered. This information is then used to select a few execution slices using a statistical classification method. In this paper, we present our approach and apply it to data cache simulation. On the SPEC95 programs, we show that slices representing 1.46% (average upon all the SPEC95 but one) of the overall program activity are as representative as sampling using a 10% sampling ratio.
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https://hal.inria.fr/inria-00476687
Contributor : Thierry Lafage <>
Submitted on : Tuesday, April 27, 2010 - 9:04:32 AM
Last modification on : Tuesday, June 15, 2021 - 4:16:10 PM
Long-term archiving on: : Tuesday, September 28, 2010 - 1:11:38 PM

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  • HAL Id : inria-00476687, version 1

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Thierry Lafage, André Seznec. Choosing Representative Slices of Program Execution for Microarchitecture Simulations: A Preliminary Application to the Data Stream. Workshop on Workload Characterization, Sep 2000, Austin, Texas, United States. ⟨inria-00476687⟩

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