Microarchitecture simulations are aimed at providing results representative of the behavior of a processor on an application. Due to CPU time constaints, only a few execution slices of a large application can be simulated. The aim of this paper is to propose a technique to choose a few program execution slices representative of the entire execution. Precise dynamic program behavior is gathered. This information is then used to select a few execution slices using a statistical classification method. In this paper, we present our approach and apply it to data cache simulation. On the SPEC95 programs, we show that slices representing 1.46% (average upon all the SPEC95 but one) of the overall program activity are as representative as sampling using a 10% sampling ratio.