The design of high performance circuits implies the convergence of different parameters such as: short fabrication time, wide functionality, high clock frequency, low power. This induces a clever design flow for managing CAD tools with physical level defined indicators. To address this problem we used a closed form model of delay in CMOS structures to define the optimization range and set up adapted optimization circuit techniques. In this paper, we validate the design space exploration method, defining maximum and minimum delay bounds on logical paths. Then we adapt this method to a "constant sensitivity method" allowing to size a circuit at minimum area under a delay constraint. Three techniques are explored and characterized: path global sizing, local buffer insertion and mixed sizing and buffer insertion. An optimization protocol is finally defined to manage the trade-off performance constraint – circuit structure. These methods are implemented in an optimization tool (POPS) and validated by comparing the optimization results obtained on various benchmarks (ISCAS’85) to that resulting from an industrial tool.