Automatic Synthesis of Hardware Accelerators from High-Level Specifications of Physical Layers for Flexible Radio

Ganda Stephane Ouedraogo 1
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : The Internet of Things (IoT) aims at connecting billions of communicating devices through an internet-like network. To this aim, the access to these things is expected to be performed via wireless technologies without using any predefined infrastructures or standards. This technology requires defining and implementing smart nodes capable to adapt to different radio communication protocols. In this thesis, we have defined a design methodology/flow, for such smart nodes, starting from their high-level specification down to their implementation in FPGA fabrics. This flow aims at improving the programmability of the waveforms by leveraging some high-level specifications. Thus, it relies on the High-Level Synthesis (HLS) for rapid prototyping of the waveforms functional blocks as well as the dataflow model of computation. Its entry point is Domain-Specific Language which enables modeling a waveform while inserting some implementation constraints for reconfigurable architectures such as the FPGAs. The flow is featured with a compiler which purpose is to produce some synthesis scripts and generate some RTL source code. The final waveform consists of a datapath and a control unit implemented as a Hierarchical Finite State Machine (HFSM).
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https://hal.inria.fr/tel-01096012
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Submitted on : Tuesday, December 16, 2014 - 4:09:14 PM
Last modification on : Wednesday, December 18, 2019 - 5:33:53 PM
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  • HAL Id : tel-01096012, version 1

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Ganda Stephane Ouedraogo. Automatic Synthesis of Hardware Accelerators from High-Level Specifications of Physical Layers for Flexible Radio. Hardware Architecture [cs.AR]. Université de Rennes 1, 2014. English. ⟨tel-01096012⟩

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