Skip to Main content Skip to Navigation

# Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO

Abstract : This work presents a high-throughput and low-latency matrix inversion design for linear pre-coders for massive multiple-input multiple-output (MIMO) systems. Because of the large number of base station (BS) antennas, as well as the multiple user terminals (UTs), served in a massive MIMO system, the channel matrix dimensions become large. Inversions of such large matrices using direct inversion methods, such as those used in linear pre-coders, would entail prohibitive complexity. To avoid such complexity, Neumann-series-based approximate inversion has been suggested for linear pre-coders in massive MIMO systems. However the performance, complexity and convergence speed of the Neumann series approach highly depends on the initial approximation of the inverse used as a starting point. In this work, we present a novel initial approximation for the Neumann series, which facilitates the parallel computation of the inverse and hence results in lower latency for inversion as well as better accuracy when compared to the previous approaches. A VLSI architecture of the proposed method is implemented for the inversion of a $16\times 16$ matrix in TSMC 65-nm technology. A throughput of 0.54 M to 15 M matrix inversion per second is achieved at a clock frequency of 460 MHz with a 117 K gate count.
Keywords :
Domain :
Complete list of metadatas

Cited literature [18 references]

https://hal.inria.fr/hal-01675193
Contributor : Hal Ifip <>
Submitted on : Thursday, January 4, 2018 - 10:59:52 AM
Last modification on : Thursday, January 4, 2018 - 11:04:10 AM
Document(s) archivé(s) le : Thursday, May 3, 2018 - 7:09:19 AM

### File

456609_1_En_10_Chapter.pdf
Files produced by the author(s)

### Licence

Distributed under a Creative Commons Attribution 4.0 International License

### Citation

Syed Abbas, Chi-Ying Tsui. Approximate Matrix Inversion for Linear Pre-coders in Massive MIMO. 24th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSISOC), Sep 2016, Tallinn, Estonia. pp.192-212, ⟨10.1007/978-3-319-67104-8_10⟩. ⟨hal-01675193⟩

Record views

Files downloads