A Review of World's Fastest Connected Component Labeling Algorithms: Speed and Energy Estimation

—Optimizing connected component labeling is cur-rently a very active research field. The current most effective algorithms although close in their design are based on different memory/computation trade-offs. This paper presents a review of these algorithms and a detailed benchmark on several Intel and ARM embedded processors that allows to focus on their advantages and drawbacks and to highlight how processor architecture impact them.

Keywords

connected component labeling Rosenfeld Suzuki transitive closure image processing

Domains

Data Structures and Algorithms [cs.DS] Hardware Architecture [cs.AR] Signal and Image Processing Computer Vision and Pattern Recognition [cs.CV] Automatic Signal and Image processing Computer Arithmetic Distributed, Parallel, and Cluster Computing [cs.DC] Software Engineering [cs.SE] Discrete Mathematics [cs.DM] Robotics [cs.RO] Image Processing [eess.IV]

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DASIP14.pdf (544.46 Ko)

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Lionel Lacassagne : Connect in order to contact the contributor

https://inria.hal.science/hal-01081962

Submitted on : Wednesday, November 12, 2014-12:12:52 PM

Last modification on : Monday, February 12, 2024-9:46:06 AM

Long-term archiving on: Friday, February 13, 2015-10:40:29 AM

Dates and versions

hal-01081962 , version 1 (12-11-2014)

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Identifiers

HAL Id : hal-01081962 , version 1
DOI : 10.1109/dasip.2014.7115641

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Laurent Cabaret, Lionel Lacassagne, Louiza Oudni. A Review of World's Fastest Connected Component Labeling Algorithms: Speed and Energy Estimation. International Conference on Design and Architectures for Signal and Image Processing, Oct 2014, Madrid, Spain. ⟨10.1109/dasip.2014.7115641⟩. ⟨hal-01081962⟩

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