Single Base Modular Multiplication for Efficient Hardware RNS Implementations of ECC

Karim Bigou 1, * Arnaud Tisserand 1, *
* Auteur correspondant
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : The paper describes a new RNS modular multiplication algorithm for efficient implementations of ECC over FP. Thanks to the proposition of RNS-friendly Mersenne-like primes, the proposed RNS algorithm requires 2 times less moduli than the state-of-art ones, leading to 4 times less precomputations and about 2 times less operations. FPGA implementations of our algorithm are presented, with area reduced up to 46 %, for a time overhead less than 10 %.
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Communication dans un congrès
T. Guneysu and H. Handschuh. CHES: 17th International Workshop on Cryptographic Hardware and Embedded Systems, Sep 2015, Saint-Malo, France. Springer, 9293, pp.123-140, 2015, Lecture notes in computer science. <http://www.chesworkshop.org/>. <10.1007/978-3-662-48324-4_7>
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Karim Bigou, Arnaud Tisserand. Single Base Modular Multiplication for Efficient Hardware RNS Implementations of ECC. T. Guneysu and H. Handschuh. CHES: 17th International Workshop on Cryptographic Hardware and Embedded Systems, Sep 2015, Saint-Malo, France. Springer, 9293, pp.123-140, 2015, Lecture notes in computer science. <http://www.chesworkshop.org/>. <10.1007/978-3-662-48324-4_7>. <hal-01199155v2>

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