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Architecture FPGA améliorée et flot de conception pour une reconfiguration matérielle en ligne efficace

Abstract : The self-reconfiguration capabilities of modern FPGA architectures pave the way for dynamic applications able to adapt to transient events. The CAD flows of modern architectures are nowadays mature but limited by the constraints induced by the complexity of FPGA circuits. In this thesis, multiple contributions are developed to propose an FPGA architecture supporting the dynamic placement of hardware tasks. First, an intermediate representation of these tasks configuration data, independent from their final position, is presented. This representation allows to compress the task data up to 11x with regard to its conventional raw counterpart. An accompanying CAD flow, based on state-of-the-art tools, is proposed to generate relocatable tasks from a high-level description. Then, the online behavior of this mechanism is studied. Two algorithms allowing to decode and create in real-time the conventional bit-stream are described. In addition, an enhancement of the FPGA interconnection network is proposedto increase the placement flexibility of heterogeneous tasks, at the cost of a 10% increase in average of the critical path delay. Eventually, a configurable substitute to the configuration memory found in FPGAs is studied to ease their partial reconfiguration.
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Submitted on : Monday, June 27, 2016 - 11:39:10 AM
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  • HAL Id : tel-01253498, version 3


Christophe Huriaux. Architecture FPGA améliorée et flot de conception pour une reconfiguration matérielle en ligne efficace. Architectures Matérielles [cs.AR]. Université Rennes 1, 2015. Français. ⟨NNT : 2015REN1S140⟩. ⟨tel-01253498v3⟩



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