TECSCE: HW/SW Codesign Framework for Data Parallelism Based on Software Component

Abstract : This paper presents a hardware/software (HW/SW) codesign framework (TECSCE) which enables software developers to easily design complex embedded systems such as massive data-parallel systems. TECSCE is implemented by integrating TECS and SCE: TECS is a component technology for embedded software, and SCE provides an environment for system-on-a-chip designs. Since TECS is based on standard C language, it allows the developers to start the design process easily and fast. SCE is a rapid design exploration tool capable of efficient MPSoC implementation. TECSCE utilizes all these advantages since it supports transformation from component descriptions and component sources to SpecC specification, and lets the developers decide data partitioning and parallelization at a software component level. Moreover, TECSCE effectively duplicates software components, depending on their degree of data parallelizing, to generate multiple SpecC specification models. An application for creating a panoramic image removing objects, such as people, is illustrated as a case study. The evaluation of the case study demonstrates the effectiveness of the proposed framework.
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Takuya Azumi, Yasaman Syahkal, Yuko Hara-Azumi, Hiroshi Oyama, Rainer Dömer. TECSCE: HW/SW Codesign Framework for Data Parallelism Based on Software Component. 4th International Embedded Systems Symposium (IESS), Jun 2013, Paderborn, Germany. pp.1-13, ⟨10.1007/978-3-642-38853-8_1⟩. ⟨hal-01466675⟩

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