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VLSI-SoC: Forward-Looking Trends in IC and Systems Design 18th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2010 Madrid, Spain, September 27-29, 2010 |
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Conference papers
Design and Optimization of a Digital Baseband Receiver ASIC for GSM/EDGE
Abstract : This paper addresses complexity issues at algorithmic and architectural level of digital baseband receiver ASIC design for the standards GSM/GPRS/EDGE, in order to reduce power consumption and die area as desired for cellular applications. To this end, the hardware implementation of a channel shortening pre-filter combined with a delayed decision-feedback sequence estimator (DFSE) for channel equalization is described. The digital receiver back-end including a flexible Viterbi decoder implementation is presented and hardware savings that can be achieved by using hard-decisions are discussed. Design trade-offs are highlighted to prove the efficiency of the implemented 2.5G multi-mode architecture. The ASIC in 0.13 μm CMOS technology occupies 1.0 mm2 and dissipates only 1.3 mW in fastest EDGE data transmission mode.
Cited literature [22 references]
https://hal.inria.fr/hal-01515990
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Submitted on : Friday, April 28, 2017 - 2:29:43 PM
Last modification on : Thursday, March 5, 2020 - 5:40:18 PM
Long-term archiving on: : Saturday, July 29, 2017 - 1:36:34 PM
Contributor : Hal Ifip Connect in order to contact the contributor
Submitted on : Friday, April 28, 2017 - 2:29:43 PM
Last modification on : Thursday, March 5, 2020 - 5:40:18 PM
Long-term archiving on: : Saturday, July 29, 2017 - 1:36:34 PM
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